As the gate length of the field-effect transistor is reduced, short-channel effects such as drain-induced barrier lowering are worsened and off-state leakage current is increased. To suppress short-channel effects and to reduce off-state leakage current, the equivalent silicon oxide thickness (EOT) needs to be scaled down. For the field-effect transistors with gate lengths well below 20 nm, the EOT needs to be reduced below 1 nm.
Reducing the EOT by reducing the physical thickness of a given dielectric material increases the gate leakage current density, which is undesirable, as the gate leakage current density needs to be kept in check within certain limits. By adopting a gate dielectric with a higher dielectric permittivity or k value, the physical thickness of the gate dielectric material can be increased for a given gate capacitance density, and the gate leakage current density can be effectively suppressed.
High-k value gate dielectric is used with metal gate electrodes in advanced Complementary Metal-Oxide-Semiconductor (CMOS) technology generations to enable the further scaling of the transistor gate length while controlling short-channel effect. A common high-k value gate dielectric used in the industry is hafnium oxide (HfO2) with a k value of about 20 or higher. HfO2 is commonly formed on an interfacial layer comprising SiO2, which is formed using atomic layer deposition. Hafnium silicate (HfSixOy) with a medium k value of about 10 may also be used.
The total EOT of a gate dielectric stack including a high-k value gate dielectric on an interfacial layer is equal to the sum of the EOT of the high-k gate dielectric and the EOT of the interfacial layer. To reduce the EOT of the gate dielectric stack, a gate dielectric material with a k value higher than that of HfO2, such as lanthanum oxide or other dielectric materials with k value larger than 25, may be used in the gate stack. Alternatively, the thickness of the interfacial layer may be reduced or eliminated by scavenging oxygen from it. In other approaches for reducing the EOT, the permittivity of the interfacial layer may be increased.
In above-mentioned approaches, the interface state density should be kept low (preferably close to or below 1011/cm2eV) to prevent the degradation of the carrier mobility in the channel, and the gate stack reliability should not be worsened.